Design-Reuse

Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro

Hamamatsu City, Shizuoka, Japan -- Sept 19, 2007-- Fujitsu Limited and Denali Software, Inc. today announced their co-development of a DDR DRAM physical interface (DDR PHY) product compatible with the ...
Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
EDN

Design tool yields DDR memory interface IP

The DDR PHY compiler is said to be the industry’s first DDR SDRAM design tool. It enables assembly of a complete, customized high-performance DDR PHY for ASICs, ASSPs, or SoC applications while ...
Electronic Design

DDR3 and DDR2 Memory IP Bolsters SoC Designs

A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare ...
EDN

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
Business Wire

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd ...