EDN

New error comparison scheme proposed for design rule checking flows

BENGALURU, India — With design rule checking becoming hugely complex in the deep sub-micron regime, there is a large run time for physical verification tools, for the number of design rules that must ...
Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
Electronic Design

Signoff Evolves From Design-Rule Checking To Yield Analysis

IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...
Semiconductor Engineering

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows ...
Semiconductor Engineering

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts.
EDN

Tanner adds design tool

SANTA CRUZ, Calif. — Providing a low-cost alternative for IC design rule checking (DRC), Tanner EDA this week (Jan. 12) is introducing HiPer Verify, the first product in the company's new HiPer line ...