Design-Reuse

FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus

DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the ...
Design And Reuse

CAST Introduces PDM-to-PCM IP Core for Easy Interfacing of Digital Microphones with SoCs

New core enables hardware conversion of mono or stereo PDM streams to PCM, with configurable audio processing and flexible ...
Electronic Design

Solutions Mitigate Mixed-Signal SoC Implementation Headaches

The concept of silicon realization, as defined in the Cadence EDA360 vision paper, represents everything required to produce a system-on-a-chip (SoC) design in silicon. 1 Silicon realization addresses ...
Electronic Design

Massive Chiplet-Based FPGA Designed to Make More Chips

What is the Versal Premium Series? What are super logic regions (SLRs)? Why the VP1902 is important to EDA chip emulation and verification. 1. AMD’s Versal Premium FPGA system-on-chip is built around ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...